Current microprocessor designs have emphasized the need to centralize data transfer operations under control of integrated functional units that have been variously called data transfer controllers or enhanced direct memory access (EDMA). This application concerns EDMA designs employing a hub-and-port style architecture. Such EDMAs feature a hub unit, which maintains a queue of transfer requests and provides priority protocol and proper interfacing for the handling of a large number of such requests. Secondly, hub-and-port EDMAs have one or more hub interface units (HIU), each providing a seamless interface between the EDMA hub and its ports. These ports include application units (AU) peripherals.
FIG. 1 illustrates the essentials of a prior art microprocessor system having a CPU 101 and a transfer controller 102 as part of an EDMA 103. The transfer controller 102 is connected to one or more hub-interface-units (HIU) 104, 105, and 106. HIUs 104, 105 and 106 are connected to a plurality of several varieties of application-unit-interface (AUI) functions blocks 107, 108, and 109. A wide variety of application units known more commonly as peripheral units having significant performance ranges and having a variety of functional requirements are shown represented by blocks 117, 118, and 119. Some peripheral units only receive data under control of the EDMA and these have no need to generate data transfer requests. Peripheral unit 117 connected to AU interface 107 is one such peripheral. Other peripheral units, such as PUs 118 and 119, generate and communicate data transfer requests to the transfer controller 102. Inputs 113 and 114 from respective peripheral units 118 and 119 initiate the transfer requests generated in transfer request generator block 111. These transfer requests are passed to the transfer controller 102 via path 112.